1. Field
Embodiments of the invention relate to a semiconductor device.
2. Description of Related Art
A semiconductor material (hereinafter, wide bandgap semiconductor material) having a bandgap that is wider than that of silicon has a critical electric field strength that is greater than that of silicon and therefore, is expected to be a semiconductor material that may sufficiently reduce ON resistance. Further, for power semiconductor devices that use a wide bandgap semiconductor material, low ON resistance is demanded and in a vertical metal oxide semiconductor field effect transistor (MOSFET), a trench gate structure that structurally facilitates low ON resistance characteristics is adopted.
A trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed at a front surface of a semiconductor substrate. While a trench gate structure enables lower ON resistance by a reduction of cell pitch, due to the reduction of the cell pitch, decreases in breakdown voltage and increases in the electric field applied to a gate insulating film in an OFF state occur and thus, it is important to suppress these occurrences. Further, with a trench gate structure, a channel (n-type inversion layer) is formed along a trench side wall in a vertical direction (a depth direction). Therefore, channel shortening by ion implantation, epitaxial growth, etc. is facilitated as compared to in a planar gate structure in which a MOS gate is provided in a plate-like shape on the front surface of the semiconductor substrate.
A conventional semiconductor device will be described taking, as an example, a case in which silicon carbide (SiC) is used as the wide bandgap semiconductor material. FIG. 38 is a cross-sectional view of a structure of the conventional semiconductor device. The conventional semiconductor device depicted in FIG. 38 is a trench gate MOSFET fabricated using a semiconductor substrate 110 that contains silicon carbide and in which silicon carbide layers that constitute an n−-type drift region 102 and a p-type base region 104 are sequentially formed by epitaxial growth on an n+-type starting substrate 101 that contains silicon carbide. A thickness t101 of the p-type base region 104 is reduced, whereby a channel length L becomes shorter, enabling channel shortening.
First and second p+-type regions 121, 122 are selectively provided at positions deeper toward a drain than is a bottom of a trench 107, from a front surface of the semiconductor substrate 110. The first p+-type region 121 underlies the bottom of the trench 107. The second p+-type region 122 is selectively provided between (mesa region) the trench 107 and an adjacent trench 107, and is separated from the trenches 107. Provision of the first and the second p+-type regions 121, 122 realizes suppression of the electric field applied to the gate insulating film in the OFF state and enhanced breakdown voltage. Reference numerals 103, 105, 106, 108, 109, 111 to 113 are an n-type current diffusion region, an n+-type source region, a p++-type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode, respectively.
A method has been proposed as a method of suppressing short channel effect. According to the method, in a part of a well region of a planar gate MOSFET, the part being directly below the gate electrode, a region having an impurity concentration that is made higher than that of the well region is formed from an oblique direction relative to a front surface of a semiconductor substrate, using the gate electrode as a mask (for example, refer to S. Zanchetta, et al, “Analytical and numerical study of the impact of HALOs on short channel and hot carrier effects in scaled MOSFETs”, Solid State Electronics, Elsevier Science Ltd., 2002, Vol. 46, No. 3, pp. 429-434).
Further, a device has been proposed as a planar gate MOSFET that suppresses the short channel effect. The device includes at a lower part of an n−-type source region, a p-type halo region that suppresses spreading of an impurity from a source to a channel formation region (for example, refer to Japanese Laid-Open Patent Publication No. 2013-012669 (paragraph 0234)).
Further, a device has been proposed as a trench gate MOSFET that suppresses the short channel effect. The device includes in a p-type base region, a region that is separated from a gate insulating film (gate trench) and that contains a p-type impurity at a high concentration (for example, refer to Japanese Laid-Open Patent Publication No. 2015-153893 (paragraphs 0079, 0090, FIGS. 10, 12)).
Further, a device has been proposed as a planar gate MOSFET in which the ON resistance is reduced. The device includes at a part of an n−-type drift region, the part being sandwiched between a pair of p-type base regions, a field plate of a trench gate structure and an n-type low resistance region covering the field plate entirely (for example, refer to Japanese Laid-Open Patent Publication No. 2012-209330 (paragraphs 0053 to 0054, FIG. 6). In Japanese Laid-Open Patent Publication No. 2012-209330, punch-through breakdown voltage is enhanced by a field plate effect, whereby application of a structure in which the n-type low resistance region is disposed is facilitated and the ON resistance is reduced.
Further, as another conventional trench gate MOSFET, a device has been proposed that includes a p-type region that is separated from a gate trench and adjacent to a p-type base region along a direction parallel to a substrate front surface. The p-type region is in contact with an end of a p-type contact region, the end being toward a drain. An impurity concentration of the p-type region is higher than that of the p-type base region (for example, refer to Japanese Laid-Open Patent Publication No. 2008-288462 (paragraphs 0009 to 0013, FIG. 1)). In Japanese Laid-Open Patent Publication No. 2008-288462, the channel length is shortened and the ON resistance is reduced. In addition, the p-type region whose impurity concentration is higher than that of the p-type base region is provided adjacent to the p-type base region along a direction parallel to the substrate front surface, whereby punch-through of the p-type base region is prevented by the short channel effect.